Catapult High-Level Synthesis and Verification
Customers Discuss their Real-World use of HLS
The past several years have seen an explosion in the adoption of HLS for chip design driven by increasing design and verification complexity as well as time to market pressures. HLS enables designers to get their chips to market faster by shortening the overall design and verification flow.
Catapult High-Level Synthesis Solutions
Catapult Synthesis solutions from Siemens deliver C++ and SystemC language support, FPGA and ASIC independence, ASIC power estimation and optimization plus the latest in Physically aware multi-VT area and performance optimization.
C++/SystemC Synthesis
A comprehensive HLS solution covering all your needs for the most complex ASIC and FPGA designs.
Low-Power Solutions
When it comes to early architecture power estimation, plus optimizing for low-power ASIC RTL, Catapult has what you need.
Physically Aware HLS
As geometries shrink, Catapult keeps pace with design portability, physical downstream data, and exceptional Quality of Results.